Integrated circuits are often formed using fabrication steps that include diffusion processes. Photolithography is one method used to diffuse impurities into silicon to create regions of differing doping densities. Diffusion processes can leave impurity concentrations that make it difficult to manage concentration profiles and can result in lower resistivities which lead to less than optimal breakdown voltages for isolating structures.
Epitaxial or “epi” layers have a much lower level of impurities than diffused layers. Epi layers are layers of semiconductor material having the same crystalline orientation as the host substrate on which it is grown—i.e., the epi layer is a single-crystal layer having a constant doping profile (unlike that created by diffusion or implantation) which is necessary for the formation of some semiconductor devices. One result is that an epi layer has a higher resistivity than typical diffused or implanted layers. Some epi layers are deposited after initial diffusion processes to leave a “buried layer” often used in making integrated circuits such as bipolar junction transistors (BJTs). Processes that create a single-crystal epitaxial layer from deposited material are somewhat complex and involve the use of a “seed crystal” that allows an annealing process to align the crystals of the deposited material to create a single-crystal material from deposited (non-single-crystal) material.
Designers of integrated fabrication processes continuously strive to reduce device feature sizes; especially in the area of memory devices. The present inventor has recognized a need for improved feature sizes of isolation structures in the fabrication of integrated circuits.